Patent US 4,054,945

An electronic computer comprises a memory for a plurality of list components, each comprising pointer and data fields. A single instruction specifies a base and a hardware register and contains an offset datum. Particular data fields, one in each list component, contain particular data, respectively, which are to be searched by the instruction as a queue. Particular pointer fields, one in each list component, contain pointers, respectively, each pointer specifying relative to the content of the base register the particular pointer field of the list component. The pointer field includes the datum that next follows in the queue a particular datum included in a list component together with the pointer. Responsive to the contents of the base and hardward registers, a control unit of the computer successively reads the pointers and loads the hardward register with the successively read-out pointers, one at a time. Responsive to the contents and the offset datum, the control unit reads the particular data sequentially in the order of the queue.