Patent US 4,062,001

A dynamic semiconductor memory cell which can be used in content addressable or associative memories is described. In the memory cell, a one is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a first storage electrode, and a zero is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a second storage electrode. The match zero operation is performed by extracting some of any of the minority carriers stored beneath the first storage electrode, which induces a relatively small potential change on that electrode if a zero is stored in the memory cell and induces a relatively large potential change on that electrode if a one is stored therein. Similarly, the match one operation is performed by interrogating the minority carriers stored in the potential well beneath the second storage electrode. In a memory, the storage electrodes of a plurality of memory cells are "or" tied by connecting them in common.