Patent US 4,079,455

Two-unit architecture for a microprocessor having one unit to execute program instructions and another unit to fetch the instructions in their proper sequence, being arranged to permit the overlap of fetch and execute cycles to increase program execution speed. Each unit includes a register array for storing operands or addresses, each array having two independent read ports and two independent write ports. In the execution unit, the register array stores operands, read from a memory by the fetch unit, which are applied to an arithmetic-logic unit (ALU), and stores the result from the ALU. In the fetch unit, the array is used to store indirect addresses, which can be incremented or decremented in an adder.