Patent US 4,092,639

A digital to analog converter is disclosed wherein two current outputs are provided, one the complement of the other. The digital to analog converter includes a novel two branched, symmetric, transistor switching circuit as well as an improved electrical n-bit weighting network which has ports for communicating weighted signal segments to connected transistor switching circuits. Logic inputs to the switching circuits determine whether an output signal is to be supplied in a first output summing line or a second, complementary, output summing line, both of which have high output impedance and high output voltage compliance which defines true current output.