Patent US 4,092,665

Address codes are serially applied to parallel word-oriented memory banks, such as read-only memories, to read out successive sets of fixed length data words and control words in parallel. The data words contain variable length data, and the control words distinguish between the relevant and irrelevant bits of the data words. A stripper circuit responds to the data words and control words read out of the memory banks by extracting the variable length data from the data words under the control of the control words. One application for this system is in a run length encoder wherein the address codes are generated in response to the runs which are to be encoded, and the data words contain variable length message codes for representing those runs in encoded or compressed form.