Patent US 4,100,495

An incoming data stream in the output of a demodulator and its derivative in the output of a differentiator are passed by respective sampling gates to a pair of equalizers operating by recursive filtration. The optimized data pulses issuing from the first equalizer are quantized and, after storage in a shift register, are algebraically combined in a first adder with a reference signal x from that equalizer representing the vector sum of weighted data pulses from a succession of N preceding clock cycles; a resulting error signal e.sub.n is delivered to three cumulative multipliers forming part of three feedback loops which supply an optimized phase signal .zeta. to the demodulator, an optimized timing signal .tau. to the sampling gates and an optimized gain coefficient K to the equalizers. These three multipliers respectively receive the reference signal x from the first equalizer, an optimized differential signal dx/d.tau. from the second equalizer and an updating signal z from the first equalizer. A further cumulative multiplier forms part of a fourth feedback loop delivering an optimized channel coefficient G to the equalizers, this latter loop including a second adder which synthesizes another error signal e' from the incoming data pulses z and from the complex product G.multidot.x produced by the last-mentioned multiplier. Each feedback loop includes a selective delay circuit effective only during an operating phase, in contrast to an acquisition phase during which the first adder receives a locally generated test signal in lieu of the quantized data pulses.