Patent US 4,153,939

An incrementer circuit receives m digit binary input signals and derives m digit binary output signals. First to (m-1)th carry signals are generated, and the h-th (where h is integer between 2 and m-1) carry signal generator includes a transfer gate which transfers one of th (h-1)th carry signal and a reference signal in response to the h-th digit input signal as the h-th carry signal. The incrementer circuit is characterized by low power consumption and low propagation delay.