Patent US 4,189,739

An input voltage overload protection semiconductor structure useful with MOS circuitry consists of a p-region in an n-substrate with p+ type regions formed on both sides of the p-region and an n+ type region centrally located in the p-region. Input signals are applied to the first p+ region. The gate of an MOS structure to be protected from voltage overload is connected to the second p+ type region. A power supply used with the MOS structure is connected to the n+ region. This structure provides significantly greater load protection than the standard resistor-diode-resistor circuit.