Patent US 4,247,891

In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of leading zero digits of an operand on the cycle in which the operand word is processed through the decimal unit and sends that count to the execution unit in response to a predetermined microword. The apparatus counts the number of leading zero digits by first storing in a register the number of words the decimal unit will not send for processing as determined by an instruction descriptor. As the operand is received by the decimal unit, most significant word first, the number of leading zero digits in the operand is added to the register on the same cycle the operand word is processed through the decimal unit, thereby generating a count of the number of zero digits in the operand that the decimal unit will send for processing. This leading zero digit count is available to the firmware in response to a microword command.