Patent US 4,295,064

A push-pull driver circuit wherein the input signals is applied to turn on one of two transistors mounted in series and the inversion of that signal is applied to the second transistor in the series path and the output taken from between them operates to isolate the load and since one and only one of the two transistors in the series path is conducting there is a path to charge and discharge the load capacitance but no path through both devices for power dissipation. The driver circuit can be built into a 2-bit partitioning circuit which in turn, when used with a programmed logic array and the relative capacitance of the various parts being isolated from each other by a coupling circuit, the resulting assembly provides a high performance programmed array logic device.