Patent US 4,336,601

A Rewritable Programmable Logic Array (R-PLA) which can alter dynamically logic functions during processing by loading a word pattern of bit personalities to realize the specific logic functions into memory cells of Current Mode Logic (CML) is constructed by splitting a conventional Random Access Memory (RAM) of CML into two parts (SEARCH and READ parts). Each cell structure of the new R-PLA is identified with that of the conventional RAM, differing from a complicated cell structure of a flip-flop and AND gate proposed in the past. SEARCH and READ parts of the new R-PLA can operate AND functions without using special AND gates in each cell in the READ mode and can enter WRITE data from a word direction in the WRITE mode. Each part of the R-PLA comprises a two-channel selector to select READ inputs or WRITE inputs, a CML memory array and sense-drive circuits. The selector and the sense-drive circuits are controlled by means of READ/WRITE control circuits. The logic-in-memory for the AND functions on the array can be conducted by using one of multi-emitters of a transistor in each CML memory cell and an emitter of a reference transistor in each of the sense-drive circuits in the READ mode of the new R-PLA. The new READ/WRITE control circuits let a word pattern of the bit personalities load into the CML memory cells in the word direction.