Patent US 4,337,519

Patent №

US 4,337,519

Granted

—

Owner

—

Lab

—

AI components

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

06115619

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An arithmetic unit which enables speedup of operation in a system for division and/or multiplication by setting specific logical conditions for a decoder. Such specific logical conditions allows elimination of adding means which are essential in known arithmetic units to constitute the division and multiplication system in combination with the decoder.

AI hardwareG06F 7/544G06F 7/523G06F 7/535G06F 7/5375G06F 2207/5351

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AI hardware0.97

Vision0.04

Machine learning0.02

Evolutionary computation0.00

Natural language0.00

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Planning0.00

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Cited by (6)

NARROW DATA PATH FOR VERY HIGH RADIX DIVISIONUS 7,167,891 · 2007 CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATAUS 6,341,327 · 2002 NUMERIC PROCESSOR INCLUDING A MULTIPLY-ADD CURCUIT FOR COMPUTING A SUCCESSION OF PRODUCT SUMS USING REDUNDANT VALUES WITHOUT CONVERSION TO NONREDUNDANT FORMATUS 5,659,495 · 1997 COORDINATE ROTATION DIGITAL COMPUTER PROCESSOR (CORDIC PROCESSOR) FOR VECTOR ROTATIONS IN CARRY-SAVE ARCHITECTUREUS 5,317,753 · 1994 A MULTIPLY AND DIVIDE UNIT FOR A HIGH SPEED PROCESSORUS 4,665,500 · 1987 Patent US 5,493,521US 5,493,521

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