INTEGRATED LOGIC CIRCUIT ADAPTED TO PERFORMANCE TESTS

An easily testable integrated logic circuit utilizes a plurality of flip-flops to form a feedback shift register. In some embodiments, means are provided for selectively forming the flip-flops into a feedback shift register and for selectively supplying either the flip-flop contents or a random signal as partial inputs to the combinational logic circuit. In other embodiments, the feedback shift register is coupled to the AND logic array outputs of a combinational circuit which also includes an OR logic array.