Patent US 4,366,557

A circuit arrangement recognizes predetermined binary values of a specific minimum duration. Data from a plurality of data sources are emitted to a common data line by way of a respective switch. An address generator periodically generates data source addresses which are emitted, on the one hand, to a respective counting device and, on the other hand, to an address decoder. The address decoder decodes the data source addresses and generates corresponding switching signals which connect the data sources to the data line in temporal succession by way of the switches. The counting devices assigned counter readings to all data sources, the counter readings being changed by respective unit upon identification of the predetermined binary values. Upon attainment of predetermined counter readings, recognition signals and the assigned data source addresses are emitted.