PARALLEL ANALOG-TO-DIGITAL CONVERTER

In a parallel analog-to-digital converter wherein the comparator inputs are switched between +1/2 the voltage corresponding to the least significant bit and -1/2 said voltage. There is provided a bipolar differential amplifier-like circuit with a resistor connecting the collectors of the two transistors and a constant current source disposed in the emitter circuit. The comparator inputs are provided with the analog signal through said resistor, while the base of one of said transistors is provided with a clock signal having one-half the frequency of the converter clock signal.