MOS BOOTSTRAPPED BUFFER FOR VOLTAGE LEVEL CONVERSION WITH FAST OUTPUT RISE TIME

A buffer circuit (10) receives a TTL input signal at an input node (12) and produces an MOS logic signal at an output node (38). A capacitor (22) is precharged by a precharge signal (PC) to a high voltage state and a control node (32) is precharged to a high voltage state. An input transistor (14) receives a reference voltage which is a function of the levels of the TTL input. When the TTL input is high the transistor (14) is nonconductive thereby maintaining the charge at the control node (32) to render conductive a pull-down transistor (36) which drives the output signal at the output node (38) to a low state. When the TTL input signal goes to a low voltage state the input transistor (14) is rendered conductive by discharging a terminal of the capacitor (22). A second terminal of the capacitor (22) is driven to a lower voltage state to render conductive a discharge transistor (30) which connects the control node (32) to the node ( 24) connected to capacitor (22). This serves to discharge the control node (32) thereby turning off the pull-down transistor (36) and permitting a pull-up transistor (40) to drive the output node (38) to a high voltage state. The buffer circuit (10) functions as an inverter and provides a rapid transition of the output signal in response to a transition of the input signal.