METHOD OF AND SYSTEM FOR EVALUATING BIT ERRORS IN TESTING A SIGNAL PATH

Patent №

US 4,428,076

Granted

1984-01-24

Filed 1981

Owner

WANDEL & GOLTERMANN GMBH & CO. KG.

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

06330719

In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

PlanningH04L 1/242H04L 1/241

AI classification

Planning0.90
AI hardware0.00
Natural language0.00
Knowledge representation0.00
Vision0.00
Machine learning0.00
Speech0.00
Evolutionary computation0.00

Ownership

WANDEL & GOLTERMANN GMBH & CO. KG.

assignment · 39680628

Assignors

SCHUON, EBERHARD

On an employer assignment, the assignors are typically the inventors.

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