PIPELINED MICROPRAGRAMMED DIGITAL DATA PROCESSOR EMPLOYING MICROINSTRUCTION TASKING

A pipelined microprogrammed data processing system is provided having a three-stage pipelined architecture implemented so as to in effect provide for the execution of a plurality of microinstructions using three separate processors operating 120 degrees out of phase with one another and sharing the same physical hardware. Synchronized microinstruction tasking and dynamic resource allocation are also provided in the system to provide both multiprogramming and multiprocessing on a microinstruction level.