Patent US 4,493,048

A systolic array system of inner product step processors is provided in the form of a mesh connected network which rhythmically compute and pass data through the system. Each processor in the system regularly feeds data in and out, each time performing some computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be readily and efficiently pipelined on systolic array network systems according to these inventions. Such arrays enjoy simple and regular communication paths and the individual processors in the networks are substantially all identical. Similar hexagonally connected processors can, for example, optionally perform matrix multiplication and LU-decomposition of a matrix. Linearly connected systolic arrays are useful for performing a variety of other computations.