CIRCUIT ARRANGEMENT FOR SERIAL DIGITAL FILTERS

Such digital filters process digital input data occurring during short pulses of a filter sampling signal (fa) in the pure binary code and in two's complement notation. They contain a parallel-to-serial converter (pw) at the input end, at least one adder (ad), at least one shift register used as a status register (z), at least one multiplier circuit (m1) to which an input-data-dependent signal and a factor which is constant at least during the multiplication are applied as a multiplier and a multiplicand, respectively, and a serial-to-parallel converter (sw) at the output end. The status register (z) has, in addition to a number of stages determined by the number of digits of the input data, a number of stages equal to the number of digits of the multiplicand. The parallel-to-serial converter (pw) is followed by a digit complementer (se) which increases the number of digits of the output signal of the parallel-to-serial converter (pw) to that of the status register (z). The function of the multiplier circuit is implemented with a sign-signal repeater (vw) and a tap on at least one stage (r) of the status register (z) which tap is connected to the input of the sign-signal repeater (vw). Associated with the outputs of the digit complementer (se), the status register (z), and the sign-signal repeater (vw) are the inputs of the adder (ad) and the subtracter (s), or vice versa. Particularly advantageous circuit structures for the stages of the above-mentioned subcircuits are provided for implementation in ratio-type dynamic insulated-gate field-effect transistor technology using a two-phase clock system.