Patent US 4,584,661

A multi-bit arithmetic logic unit having a fast carry-look-ahead (CLA) system comprises logical preparation (LLP) circuitry of the first CLA level which interconnects several bit positions so as to output intermediate combination signals which are a function of a plurality of bit positions, rather than of a single bit position. In addition, the carry-in signal (C.sub.IN) into the least-significant-bit (LSB) of the respective group is separated from the intermediate combined propagated carry signal (C.sub.p) between groups, and is introduced into the input of the LLP circuitry of the first CLA level, combined with the LSB signals, and also with a binary "split" signal whose state determines whether the C.sub.IN is to be inputted or not. In addition, the ALU may be comprised of a plurality of identical integrated circuit chips called Y-chips, each including LLP and logical combination (LLC) circuitries of two CLA levels having reverse input-output logic such that a plurality of such chips may be connected together to form a two-level CLA, and may also be connected together, with the addition of further chips, called Z-chips, having a one-level CLA, to produce three-level, or higher-level, CLA systems.