Patent US 4,587,632

A computer architecture is disclosed which obtains the advantages of stack oriented machines from a programming viewpoint and, at the same time, obtains the hardware advantages of a multiple operand architecture from the hardware viewpoint. This is accomplished by circuitry (13) which accepts stack oriented reverse-polish instruction tokens from the memory (10) and, by using a lookahead technique (23), optimizes the generation of storage-to-storage type instructions which are then executed by the storage-to-storage hardware configuration (14).