DIGITAL PHASE LOCKED LOOP

The loop uses a phase comparator (PD) designed to compare the phase of a reference signal (F.sub.1) with the phase of a signal generated locally (F.sub.2) and also to make available on a first output (E) a signal expressing the entity of phase shift and on a second output (S) a signal expressing the sign of the phase shift (F.sub.1 leading, or lagging, in respect to F.sub.2). Thanks to the presence of this latter signal (S) it is possible to render the remaining units of the loop particularly simple and economic without having to make use of components that introduce in their turn limits in operational speed, excepting of course those imposed by the type of technology used. This loop is suitable to be conveniently implemented in an integrated manner.