WIRED LOGIC VOTING CIRCUIT

A wired voting circuit is described providing an output which follows the majority of input logic levels according to the equation: F=AB+AC+BC. A non-inverting signal voting node (D) and an inverting signal voting node (E) comprise a first and a second collector of an odd number of input differential transistor pairs (30, 32, 34) wherein said nodes are formed by wiring all of said first collectors together at one signal node and by wiring all of said second collectors together at the other signal node. Each signal node is coupled to a differential input of an output differential transistor pair (36). Currents are steered by the state of input logic onto either of the signal nodes, depending upon the input logic signal level. The signal level at each voting node is proportional to the number of input differential transistor pairs that steer current to the voting node. The voting scheme employs an odd number of logic inputs (T, U, V), such that an odd number of currents (I.sub.x, I.sub.y, I.sub.z) are steered to the voting nodes. Therefore, the signal level at a first voting node is never equal to that of the other voting node during a steady state condition; the signal level difference between the two voting nodes is indicative of the majority state of the input logic signals. An output differential transistor pair compares the signal level difference and translates it to voltage levels compatible with other signals in the system in which the invention is used. By providing redundant signal pathways, signal processing reliability is enhanced. Monolithic device yields are improved by providing for diagnosis of faulty signal pathways and elimination thereof.