BUSY SIGNAL INTERFACE BETWEEN MASTER AND SLAVE PROCESSORS IN A COMPUTER SYSTEM

Patent №

US 4,648,034

Granted

1987-03-03

Filed 1984

Owner

ZILOG, INC., A CORP. OF CA

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

06644868

A 32-bit central processing unit (CPU) having a six-stage pipeline architecture with an instruction and data cache memory and a memory management units, all provided on a single, integrated circuit (I.C.) chip. The CPU also contains means for controlling the operation of a separate I.C. chip co-processor that is dedicated to performing specific functions at a very high rate of speed, commonly called an extended processing unit (EPU). The EPU is provided with interface circuits that generate control signals and communicate them to the controlling CPU.

AI hardwareG06F 12/1045G06F 9/3881G06F 12/0802G06F 15/7832

AI classification

AI hardware1.00
Natural language0.00
Vision0.00
Evolutionary computation0.00
Machine learning0.00
Speech0.00
Knowledge representation0.00
Planning0.00

Ownership

ZILOG, INC., A CORP. OF CA

assignment · 43070764

Assignors

HENINGER, ANDREW G.

On an employer assignment, the assignors are typically the inventors.

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