FLEXIBLE CHAINING IN VECTOR PROCESSOR WITH SELECTIVE USE OF VECTOR REGISTERS AS OPERAND AND RESULT REGISTERS

A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.