APPARATUS FOR THE SIMULATION OF THE FAILURE OR SATISFACTORY OPERATION OF A LOGIC SYSTEM

An apparatus for simulating the failure or satisfactory operation of a system having a plurality of interconnected components. These components are subject to events, such as failures or repairs appearing in a sequentially combined manner. The apparatus comprises a group of simulation means representing the component to be simulated and each having at least one simulation input. The repair or failure state of the component is represented by a signal supplied on at least one output of the simulation means. This signal has a first or a second logic state respectively corresponding to the repair or failure of the component. The apparatus also comprises means for interconnecting the simulation means in accordance with a logic representing the interconnection of the components in the simulated logic system. These interconnection means have an output supplying signals, whose logic state represents the repair or failure of the simulated system.