Patent US 4,675,836

A discrete cosine transform calculation processor, suitable for compressing a television signal, comprises a processor module consisting of four successive stages. The first stage, the input stage of the module, comprises a first adder/subtracter. The second stage comprises a second adder/subtracter with two input buses each selectively connected to an output bus of the first stage or to an output bus of an input register of the second stage, loaded from an output bus of the first or fourth stage. The third stage comprises a multiplier connected to a cosine/sine function value store and to an output bus of the second stage. The fourth stage, the module output stage, comprises a third adder/subtracter with two input buses each selectively connected to an output bus of the third stage or to an output bus of an input register of this stage loaded from the multiplier.