SPEECH PROCESSOR SYSTEM WITH AUXILIARY MEMORY ACCESS

A digital speech processor operates in parallel with a programmable digital computer to generate sequences of variable-length speech phases and pauses at the request of the computer. A speech memory region within the speech processor contains digitally-encoded speech data segments of varying length. A separate command memory region, can be loaded with a plurality of commands. When sequentially executed by the speech processor, these commands cause the processor to generate an arbitrary sequence of spoken phases and pauses without intervention by the computer. When the programmable digital computer is not operating the speech processor to synthesize spoken words, the speech and command memory regions are used as auxiliary random access memory to increase the size of the memory space of the computer.