A THREE-VOLTAGE LEVEL DETECTOR FOR INDICATING A HIGH LEVEL, MID-LEVEL OR LOW LEVEL VOLTAGE

A three-voltage level detector include an input terminal for receiving an input logic signal having either a high level, mid-level or low level voltage. A first level sensing buffer is responsive to the input logic signal for generating a first output sense voltage indicative of whether the input logic signal is either at the (a) high level voltage or (b) mid-level or low level voltage. A second level sensing buffer is responsive to the input logic signal for generating a second output sense voltage indicative of whether the input logic signal is either at the (a) high level or mid-level voltage or (b) low level voltage. Logic gate circuits are responsive to the first and second output sense voltages for generating at a first output terminal of the detector a first output signal being in a high level only when the input logic signal is at the high level voltage, at a second output terminal of the detector a second output signal being in a high level only when the input logic signal is at the low level voltage, at a third output terminal of the detector a third output signal being in a high level only the input logic signal is at the mid-level voltage.