SUB-RANGING A/D CONVERTER WITH FLASH CONVERTER HAVING BALANCED INPUT

A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.