FAST MULTIPLIER ARCHITECTURE

A digital multiplier circuit which implements a modified multiplier algorithm in binary form and can be implemented as a very large scale integrated circuit. The modified algorithm replaces the large summation required in a typical shift-and-add digital multiplier with the sum of smaller summation terms, both yielding the same product. The digital word representing one of the multiplicands is partitioned or sliced into groups of two or more bits. All possible values of each bit slice are pre-calculated and stored to derive partial products thereof by the other multiplicand. The summation of such partial products rather than of individual bit products reduces the number of partial adders by half or more, depending on the number of bits in each partition or slice.