HIGH-SPEED DIGITAL IMAGE PROCESSING APPARATUS

An image processing apparatus is provided which is capable of real time image processing, especially filtering, without generating a delay in a frame memory. A cascade filtering circuit filters digital video signals obtained by digitally converting analog video signals to obtain a time sequential digital pixel data stream for the filtering operation based on a pattern of predetermined constants of a p-rows, q-columns. The cascade filtering circuit uses p basic filter circuits (100) cascade-connected with each other. Each basic filter circuit carries out the filtering for one-row and q columns of pixel data. Each basic filter circuit (100) includes delay circuits (40, 41, 42), multipliers (20, 21, 22), and adders (30, 31, 32). Interlace type digital video signals are converted into a noninterlace type pixel data stream by a structure wherein two frame memories (85a and 85b) are alternately switched in accordance with a frame period and the pixel data are written in every other lines in one frame memory while the pixel data are read-out in a noninterlace manner from the other frame memory and vice versa.