MEMORY ACCESS CONTROL SYSTEM

A data processing system includes a memory access control unit having a cache memory, an address array, a plural storage stage recirculating address pipeline and a plural storage stage recirculating data pipeline. An address inquiry to the address array indicates whether or not corresponding data is stored in the cache memory. If the data is available from the cache memory, it is read out to a storage stage in the data pipeline and supplied to the requester. If the data is not available from the cache memory, an access request is sent to the main memory. Until there is a response from the main memory the requested address is recirculated in the address pipeline. The main memory supplies the requested data to a storage stage in the data pipeline, from which it is transferred to a requester. When data is to be written into a memory and the cache memory is not accessible, the data is recirculated in the data pipeline until access to the main memory is possible.