FULL ADDER CIRCUIT WITH IMPROVED CARRY AND SUM LOGIC GATES

First and second input gates and an input inverter are provided for preprocessing respectively a plurality of input signals and an additional input signal, in addition to a carry gate and a sum gate. The first input gate is connected to each of a plurality of input bits for providing a logic low output only when all of its inputs are a logic high. The second input gate is connected to the plurality of input bits for providing a logic high only when all of its inputs are a logic low. The carry gate has three inputs and provides a carry-out logic high output when either (a) its first input from the first logic gate is a logic low; or (b) when both the second input from the second input gate and the third input from the inverter are a logic low. The sum gate has five inputs and provides a sum logic high output when either (a) both its first and second inputs from the output of a first input gate and from the inverter are logic low; or (b) its third input from the carry gate is at a logic low and either of the fourth or fifth inputs from the inverter or the second input gate are respectively a logic low.