DATA PROCESSING SYSTEM

A data processing system includes a microcomputer (1) and a watchdog circuit arrangement which includes a clocked counter (17) having an output Q.sub.n which is coupled to a reset input (RST) of the microcomputer. In order to increase the kinds of microcomputer malfunctions to which the watchdog circuit responds, the microcomputer is programmed to repeatedly generate predetermined reset signal bytes within respective time windows, such time windows corresponding to periods during which a further output Q.sub.n-1 of the counter is logic "1". The reset signal byte supplied by the microcomputer is compared by a comparator (10) with the predetermined reset signal byte, which is supplied thereto by a switched multiplexor (13), and if they match the output signal from the comparator resets the counter. Each time this occurs the microcomputer strobes the watchdog circuit by applying its address to a further input (22, 46) thereof. If a reset signal byte should be supplied by the microcomputer outside a time window and/or if such signal byte is incorrect, the resulting signal level at the output of the comparator, which is stored in a flip-flop (15), actuates the watchdog circuit to produce an output signal which resets the microcomputer. The logic value of the Q.sub.n-1 signal from the counter is periodically ascertained by the microcomputer to determine the subsequent time window during which the next reset signal byte is to be generated.