Patent №
US 5,081,601
Granted
1992-01-14
Filed 1989
Owner
LSI LOGIC CORPORATION
Lab
—
AI components
1
evo
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
07411291
Two or more independently clocked simulators are interconnected in a manner which prevents signal exchange at a time when the internal simulation clocks of the simulators point to different times on a simulated time line. Each simulator transmits to one or more of the other simulators in its network information indicaitng the next point in simulated time at which the transmitting simulator can model a state change which might affect a model part being simulated by the receiving simulator. Blocking means are provided for blocking the receiving simulator from advancing its simulated time clock ahead of the next state change time of the transmitting simulator. The receiving simulator is free, however, to operate at its maximum speed for simulated time spans occurring before the next state change time of the transmitting simulator.
AI classification
Ownership
LSI LOGIC CORPORATION
assignment · 58480001
Assignors
EIRIKSSON, ASGEIR TH.
On an employer assignment, the assignors are typically the inventors.