INPUT/OUTPUT PROCESSOR CONTROL SYSTEM WITH A PLURALITY OF STAGING BUFFERS AND DATA BUFFERS

A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts and includes staging buffers coupled to the main bus and data buffers coupled to the data bus. A J-Bus is coupled between the staging buffers and the data buffers and is controlled by J-Bus transfer controller. A D-Bus transfer controller controls information transferred to an from the data bus and the data buffers. An M-Bus transfer controller controls information transferred to and from the staging buffers and the M-Bus. A controllable time slot generator in addition to generating the time slots for transferring information between the data buffers on the J-Bus also provides means for resolving conflicts between the J-Bus and the D-Bus and the M-Bus.