CHARGE DOMAIN VECTOR-MATRIX PRODUCT PROCESSING SYSTEM

A charge domain vector-matrix product processing system. The system includes a charge coupled device tapped delay line, an array of digital parallel shift register memory devices, and a signal processor. A sampled analog signal is stored within the tapped delay line, and multiple vectors of m-bit words are stored within the digital memory device. The signal processor sucessively applies vectors from the digital memory device and charge packets from the tapped delay line to an array of digital-analog multipliers. The signal processor then sums the outputs of the digital-analog multipliers and produces an output charge packet corresponding to a respective element of the vector-matrix product.