FLOATING GATE ARRAY TRANSISTORS

A junction field effect transistor having an array of electrically floating gate elements located between the control gate and the drain in the path of current flow from the source to the drain. As the drain voltage increases the depletion zone of the control gate expands until it reaches the nearest floating gate. The maximum electric field at the control gate is clamped while the nearest floating gate increases in potential and its depletion zone expands toward the next floating gate, and so on. In this way the applied voltage is spread over the array of floating gates clamping the maximum electric field at a value that is less than the avalanche breakdown field. Then, the avalanche breakdown voltage of the device is increased.