TRANSISTOR DEVICE WITH RESISTIVE COUPLING

A static memory cell comprises a first PMOS transistor including a drain 319, a channel 344, a source 317, and a lightly doped drain 360 and a first NMOS transistor including a source 323, a channel 346, and a drain 321. A first gate 334 insulatively overlies the channel 344 and the lightly doped drain region 360 of the first PMOS transistor as well as the channel 346 of the first NMOS transistor. The memory cell also includes a second PMOS transistor which in turn includes a drain 327, a channel 362, a source 325, and a lightly doped drain 364 and a second NMOS transistor which includes a source 323, a channel 368, and a drain 329. A second gate 338 insulatively overlies the channel 362 and the lightly doped drain region 364 of the second PMOS transistor and the channel 368 of the second NMOS transistor. A first gated resistor is coupled between the drain 319 of the first PMOS transistor and the second gate 338 and a second gated resistor is coupled between the drain 327 of the second PMOS transistor and the first gate 334. Other systems and methods are also disclosed.