Patent US 5,214,765

A primary, a secondary, and a tertiary cache, and a floating point pipeline having optimized complimentary characteristics are provided to a computer system for executing floating point instructions. The primary cache is direct mapped and having n.sub.1 cache lines, each having a cache line size of m.sub.1 floating point data word(s) and an access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integer greater than or equal to 1. The secondary cache is fully associative having n.sub.2 cache lines, each having a cache line size of m.sub.2 floating point data words and an access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1, and t.sub.2 is a small integer greater than t.sub.1. The tertiary cache has n.sub.3 cache lines, each having a cache line size of m.sub.3 floating point data words and an access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2. The tertiary cache may be direct mapped or set associative. The a floating point pipeline has a fetching phase, a decoding phase, d delay phases requiring at least t.sub.1 +t.sub.2 clock cycles, and at least one floating point execution phase.