CMOS OUTPUT BUFFER WITH PRE-DRIVE CIRCUITRY TO CONTROL SLEW RATE OF MAIN DRIVE TRANSISTORS
Patent №
US 5,216,293
Granted
1993-06-01
Filed 1991
Owner
KABUSHIKI KAISHA TOSHIBA
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
07814438
A CMOS output buffer comprises an output stage circuit including MOS transistors each having a CMOS structure, for outputting a signal, and an output stage control circuit arranged prior to the output stage circuit. The output stage control circuit includes a pull-up circuit and a pull-down circuit for controlling the gate of the final stage MOS transistor of the MOS transistors so that a speed at which a gate-to-source voltage varies when the final stage MOS transistor is turned on, is slower than a speed at which the gate-to-source voltage varies when the final stage MOS transistor is turned off.
AI classification
Ownership
KABUSHIKI KAISHA TOSHIBA
assignment · 59860595
Assignors
SEI, TOSHIKAZU, TANAKA, YASUNORI, OCHI, SHINJI
On an employer assignment, the assignors are typically the inventors.