FLOATING-POINT PROCESSOR FOR PERFORMING AN ARITHMETIC OPERATION ON FIXED-POINT PART DATA WITH HIGH SPEED ROUNDING OF A RESULT

A floating-point processor includes a carry saving adder-subtracter for generating carry data and sum data by performing addition and subtraction of a first fixed-point part having a greater exponent part and a second fixed-point part, which is aligned with the first fixed-point part by being shifted right, having a smaller exponent part according to preferably predetermined conditions. The processor also includes a rounding-carry generating circuit for generating, from a rounding-mode signal and low-order digits of the fixed-point parts, a first rounding-carry, of which the value in case of rounding the result of addition or subtraction between the fixed-point parts to a higher order digit is in agreement with that in case of rounding the result of addition or subtraction therebetween to a lower order digit, and for generating a second rounding-carry in each of the cases of rounding the result of addition or subtraction therebetween. The processor further includes an adder-subtracter for outputting a first result of addition or subtraction between data obtained by adding the first rounding-carry to the least significant digit of the carry data and the sum data and for outputting a second result of adding 1 to or subtracting 1 from the first result and an invention circuit for outputting a logical inversion of all digits of the second result and a selection circuit for selecting one of the first and second results and an output of the inversion circuit.