ELECTRICALLY ERASABLE MEMORY DEVICE HAVING ERASE-ELECTRODE CONNECTED TO SUBSTRATE JUNCTION

A nonvolatile semiconductor device according to the present invention comprises a memory cell array having memory cells arranged in a matrix, each emory cell being composed of a floating gate electrode, control gate electrode, a source diffusion layer, and drain diffusion layer, tunnel oxide films formed on the side walls of the floating gate electrodes on the side where adjacent memory cells, sharing the control gate electrode, face each other, and an erasure gate electrode formed so as to sandwich the tunnel oxide films between the floating gate electrodes and itself, and electrically connected to the source diffusion layer at nearly an equal distance from the adjacent memory cells sharing the control gate electrode.