PROCESSING SYSTEM WITH IMPROVED SEQUENTIAL MEMORY ACCESSING

A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each being addressable at a corresponding different storage address, a processor coupled to the memory for addressing the memory storage locations for accessing the storage locations and control means coupled to the memory and to the processor. The control means is responsive to a sequential access by the processor for causing the processor to address selected spaced apart ones of the storage locations in order and is arranged to access the other memory locations in order between the processor addresses to provide an access rate of one word of information per system clock cycle.