Patent US 5,250,824

Patent №

US 5,250,824

Granted

Owner

Lab

AI components

2

vision · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

07881080

Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

VisionAI hardwareG11C 19/285H04N 25/713

AI classification

AI hardware0.98
Vision0.98
Machine learning0.00
Natural language0.00
Planning0.00
Knowledge representation0.00
Speech0.00
Evolutionary computation0.00
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