DATA CACHING AND ADDRESS TRANSLATION SYSTEM WITH RAPID TURNOVER CYCLE

Patent №

US 5,283,882

Granted

1994-02-01

Filed 1991

Owner

UNISYS CORPORATION, A CORP. OF DELAWARE

+1 more

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

07660455

An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.

AI classification

AI hardware0.99
Natural language0.01
Machine learning0.00
Knowledge representation0.00
Evolutionary computation0.00
Vision0.00
Planning0.00
Speech0.00

Ownership

UNISYS CORPORATION, A CORP. OF DELAWARE

assignment · 56250016

UNISYS CORPORATION, A CORP. OF DE

assignment · 56250208

Assignors

SMITH, CHRISTOPHER E., NOBLE, ROBERT L.

On an employer assignment, the assignors are typically the inventors.

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