SQUARE ROOT EXTRACTOR

An extractor of a square root has rows of first and second arithmetic elements, the number of which is determined in correspondence with bit lengths of a number to be extracted and of the square root thereof. The first arithmetic element comprises an adder for carrying out an addition operation based on either bit data out of the number to be extracted or zero, inverted input data, and carry data, to output addition result data and carry data, first selection circuit for outputting as first output data either the addition result data, or either the bit data or zero, based on selection data, and a second selection circuit for selecting either one or zero based on the selection data to output the selected data as second output data. The second arithmetic element comprises an incrementer for adding increment carry data to increment output data to output increment carry data and increment output data, an adder for carrying out an addition operation based on inverted output data of the incrementer, either bit data out of the number to be extracted, zero, or output data, and carry data, to output addition result data and carry data, and a selection circuit for selecting one out of the addition result data and either the bit data, zero, or output data based on selection data to output the selected data as output data.