SINGLE POLY EE CELL WITH SEPARATE READ/WRITE PATHS AND REDUCED PRODUCT TERM COUPLING

Patent №

US 5,331,590

Granted

1994-07-19

Filed 1991

Owner

LATTICE SEMICONDUCTOR CORPORATION, A CORP. OF DE

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

07777769

A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

AI hardwareH10B 41/30G11C 16/0408G11C 16/0441H10B 41/35H10B 69/00G11C 2216/10

AI classification

AI hardware0.60
Machine learning0.03
Speech0.00
Vision0.00
Evolutionary computation0.00
Natural language0.00
Knowledge representation0.00
Planning0.00

Ownership

LATTICE SEMICONDUCTOR CORPORATION, A CORP. OF DE

assignment · 59360456

Assignors

JOSEPHSON, GREGG R., BOWER, DOUGLAS H., TENNANT, DAVID L.

On an employer assignment, the assignors are typically the inventors.

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